As technology scales, transistor performance is not improving accordingly. In order to increase transistor performance, various processes have been implemented to apply stress to the channel region to enhance carrier mobility. Compressive stress enhances hole mobility when applied parallel to the current flow in a PMOS transistor. One method to apply compressive stress in PMOS transistors is to remove silicon from the source and drain regions and replace it with epitaxially grown silicon germanium (SiGe). Germanium is a larger atom than silicon so the lattice constant of crystalline SiGe is greater than crystalline Si applying compressive stress to the PMOS channel region. Another method is to deposit a compressive contact etch stop layer over the PMOS transistors.
For NMOS transistors, applying tensile stress either perpendicular or parallel to the current flow enhances electron mobility. One method of applying tensile stress to the channel region in an NMOS transistor is to deposit a tensile contact etch stop layer over the NMOS transistor.
Dual stress liner (DSL) technology has been developed to deposit a compressive contact etch stop layer over the PMOS to enhance hole mobility and to deposit a tensile contact etch stop layer over the NMOS to enhance electron mobility. The compressive and tensile etch stop layers are typically formed using a PECVD silicon nitride film 20 nm to 50 nm thick. Deposition conditions may be varied to deposit either a highly compressive or a highly tensile stress silicon nitride film. Typically a compressive contact etch stop layer is deposited over the entire wafer and then patterned and etched away from the NMOS transistor regions followed by a tensile contact etch stop layer deposited over the entire wafer and then patterned and etched away from the PMOS transistor regions.
A boundary is formed where the borders of the compressive and tensile etch stop layers meet (DSL border). Typically an overlap region is formed at the border where a strip of tensile contact etch stop layer overlies the border of the compressive contact etch stop layer. The spacing of this DSL border from the PMOS active area perpendicular to the PMOS transistor gate may be adjusted to improve PMOS transistor characteristics.